The present invention relates to reducing distortion in analog circuits.
In any analog network, such as a sampling or tracking network, a large portion of the distortion (nonlinearity) is generated by the flow of non-linear current (or charge) in the source resistance/impedance that is connected as input to the sampling network. Sometimes, that impedance is located outside the die and can vary by the user or application. Therefore, devices on the sampling network have little or no control over the distortion generated.
A traditional approach to reducing the distortion was to reduce the non-linear current generated by the sampling network itself. This led to techniques such as gate bootstrapping, back-gate bootstrapping, back-gate floating, buffering, etc.
FIG. 1 shows a conventional sampling network circuit 100 implementing a gate-bootstrapping technique to reduce non-linear current generated by the sampling network 100. Sampling network 100 includes a sampling capacitor 101, a switch 106 connected to capacitor 101, a transistor 102 (M1) that connects the capacitor 101 to an input Vin, a bootstrap circuit 103 connected between Vin and a gate of transistor 102, and additional transistors 104, 105 connected to a back-gate (BG) of transistor 102.
The circuit 100 has two switches 106, 102 connected in series. Switch 106 (shown symbolically connected to the capacitor 101) is clocked by φ1a and switch 102 (M1) is clocked by φ1—btst. φ1a controls when the sample is taken. The signals φ1a and φ1—btst are offset, such that φ1a opens (goes low) before φ1—btst. By providing the bootstrap circuit between Vin and the gate of transistor 102, the voltage between the gate and the source (Vgs) of transistor 102 is fixed (meaning that the transistor's 102 resistance is also fixed). Thus, when Vin varies, the gate voltages changes by the same amount.
Linearity is also provided by connecting BG to Vin so that the voltage between the source and BG is also fixed. In this case, φ2 is opposite in phase to φ1a. During sampling φ1a is on (e.g., high), so that all switches connected to φ1a are turned on and BG is connected to Vin as a result. In the opposite phase, φ2 is on and φ1a is off, so that BG is connected to ground (this refreshes BG). The gate of transistor 102 may also be connected to a switch (not shown) controlled by φ2 to connect the gate to ground.
FIG. 2 is a an equivalent circuit 200 of the sampling network 100 of FIG. 1 during a tracking phase of operation. The sampling network 200 includes a source impedance 202 (Zs) and an input impedance 204 (Zin). Input impedance 204 is the input impedance of a sampling circuit (not shown, but similar to the sampling circuit in FIG. 1) and source impedance 202 is the source impedance of an input network (not shown) that generates Vin to drive the sampling circuit. The propagation of the input signal through the sampling circuit (which is now represented simply by Zin) to a sampling capacitance is one significant source of distortion. In addition, the non-linear component of Zin is another major cause of distortion
The voltage sampled by sampling circuit can be represented as follows:
                    Vin        =                              Vs            ·            Zin                                Zs            +            Zin                                              Eq        .                                  ⁢                  (          1          )                    If the non-linear component of Zin is ΔZin, the non-linear component of the sampled voltage may be derived as follows:
                    Vin        =                              Vs            ⁡                          (                              Zin                +                                  Δ                  ⁢                                                                          ⁢                  Zin                                            )                                            Zs            +            Zin            +                          Δ              ⁢                                                          ⁢              Zin                                                          Eq        .                                  ⁢                  (          2          )                                        Vin        =                              Vs                          1              +                              Zs                Zin                                              ⁢                      (                          1              +                                                Zs                  ·                                                            Δ                      ⁢                                                                                          ⁢                      Zin                                        Zin                                                                    Zs                  +                  Zin                                                      )                                              Eq        .                                  ⁢                  (          3          )                                                              Δ            ⁢                                                  ⁢            Vin                    Vin                =                                                            Δ                ⁢                                                                  ⁢                Zin                            Zin                                      1              +                              Zin                Zs                                              ⁢                                          ⁢          or          ⁢                                          ⁢                                                    Δ                ⁢                                                                  ⁢                Iin                            Iin                        ·                          Zs              Zin                                                          Eq        .                                  ⁢                  (          4          )                    where ΔVin is the non-linear component of the sampled voltage (i.e. distortion). This formula is general and applies to any input network (whether buffered or unbuffered).
Thus, to have a low distortion, the source impedance Zs should be low, the input impedance of the sampling circuit should be large, and the non-linearity of the input impedance ΔZin should be small and/or the non-linear current ΔIin should be small. Consequently, the performance of pipelined analog-to-digital converters (ADCs) becomes worse as their source impedance increase. Traditionally, this non-linearity could only be reduced by minimizing the input switch non-linear parasitic.
The conventional techniques described above may not adequately reduce distortion in analog systems. Thus, the inventors perceived a need in the art to further reduce distortion in analog systems.